FIG. 12 shows one construction example of a memory array for a semiconductor memory device, for example, a DRAM. In FIG. 12, the memory array is constructed by means of the word lines WL0 to WL5, bit lines (or complementary bit lines) BL0, BL0.sub.--, BL1, BL1 and the memory cells MC.sub.0,0, MC.sub.0,1, MC.sub.0,2, . . . , MC.sub.1,4, MC.sub.1,5 that are respectively connected at the intersection points of these word lines and bit lines (and complementary bit lines). In this Figure, only a portion of the memory array is shown for the purpose of explanation. The bit line pair comprising bit line BL0 and complementary bit line BL0.sub.-- are connected to the sense amplifier SA0, and the bit line pair comprising bit line BL1 and complementary bit line BL1.sub.-- are connected to the sense amplifier SA1. During memory access, the bit line and the complementary bit line comprising a bit line pair are respectively held at different voltage levels by means of the sense amplifier. For example, when the bit line BL0 is held at a high level (power supply voltage V.sub.DD level, the complimentary bit line BL0.sub.-- is held at a low level (common voltage V.sub.SS level). The word lines WL0 to WL5 are selected and driven by means of the word line drive circuit WD. In FIG. 12, the word line drive circuit WD is omitted.
The memory cells MC.sub.0,0, MC.sub.0,1, MC.sub.0,2, . . . , MC.sub.1,4, MC.sub.1,5 are arranged at the intersection points of the word lines WL0 to WL5 and the bit lines BL0, BL0.sub.--, BL1, BL1.sub.--, respectively. As is shown in the FIG.ure, the memory cells of the DRAM, for example, the memory cell MC.sub.1,1 is constructed by means of a single transistor Q.sub.1,1 and a single capacitor C.sub.1,1, the gate of transistor Q.sub.1,1 is connected to the word line WL1, and is controlled to the ON/OFF state by means of the voltage of word line WL1. During memory access, one of the word lines among the word lines WL0 to WL5 is selected by means of the word line drive circuit WD in response to the input address signal, and since the selected word line is activated and held at a high level, the transistor for the memory cell that is connected to the selected word line is held in the ON state.
For example, if word line WL1 is selected by means of the word line drive circuit WD and held at a high level, transistor Q.sub.1,1 of memory cell MC.sub.1,1 is placed in the ON state. During writing, the level of the bit line is designated in response to the write data by means of the sense amplifier at the same time as the selection of the word line. For example, bit line BL1 is held at a high level (power supply voltage V.sub.DD level), and complementary bit line BL1.sub.-- at the low level (common voltage V.sub.SS level), respectively, by means of the sense amplifier SA1. By this means, the charging voltage and the charge of the capacitor C.sub.1,1 is held as the storage data.
On the other hand, when the storage data are read from the memory cell MC.sub.1,1, the bit line BL1 and the complementary bit line BL1.sub.-- are set beforehand via the sense amplifier SA1 to a precharge of, for example, V.sub.DD /2, which is half of the power supply voltage V.sub.DD. When the word line WL1 is activated by means of the word line drive circuit WD and held at a high level, the transistor Q.sub.1,1 is placed in the ON state, the bit line BL1 and the capacitor C.sub.1,1 are shorted, and the potential of the bit line BL1 is slightly changed in response to the accumulated charge of the capacitor C.sub.1,1. By means of this slight potential change on the bit line BL1 being detected and amplified by means of the sense amplifier SA1, the storage data for the memory cell MC.sub.1,1 are read.
Accompanying the change to a large capacity for the DRAM, the memory array has been further divided into multiple subarrays (memory cell matrices), and have become a construction that arranges sense amplifier banks comprising sense amplifiers on the side of each subarray. The sense amplifier banks are constructed by means of sense amplifiers of the same number as the bit line pairs for each subarray, and each sense amplifier bank is jointly used by means of sub-arrays that are arranged on both the right and left sides. Also, means of reducing the number of sense amplifiers by means of lengthening the bit lines and widening the subarrays, a reduction of the surface area that the sense amplifier banks occupy in the entire chip is accomplished, and a reduction of the chip size is accomplished. However, the deterioration of the characteristics that accompanies an increase in the resistance and parasitic capacitance of the bit lines due to their lengthening becomes a problem. Systems such as a construction in which the bit lines are changed to tiers have been proposed for purpose of handling this.
Also, along with the advances in the change to high capacity and miniaturization of the semiconductor memory devices, the miniaturization of the elements has advanced, and the change to thin films for the purpose of low voltage operations has also advanced. In order to ensure the gate voltage tolerance of the transistors that construct the memory cell, an internal voltage V.sub.DL that is lower than the external power supply voltage in which the external power supply voltage V.sub.DD has been dropped is being used inside the memory array. Accompanying this, the lowering of the access speed has become a problem with the sense amplifier. In order to avoid this, the so-called overdrive OVD system is being used, which supplies the external voltage power supply voltage V.sub.DD to the sense amplifier for a normal fixed period, for example, the period until the bit line has reached the memory array voltage (internal operating voltage V.sub.DL).
Incidentally, because a voltage drop originating in the sense amplifier voltage wiring resistance appears between each memory cell mat with the above-mentioned overdrive system used in the past, even if it is within the same memory array block, the optimum sense amplifier overdrive amount is different between each memory cell mat.
For example, in the 64 Mb (megabit) DRAM used in the past, in order to ensure sufficient writing at the farthest end, the timing for the overdrive was optimized at the farthest end (worst case). By this means, the overdrive at the farthest end was ensured, but it became a surplus overdrive at the nearest end, and the surplus charge was discarded. In other words, at the sense amplifier for the near end, a voltage application was conducted that was greater than necessary during memory access, and there were disadvantages in that this invited the deterioration of the characteristics of the transistors that construct the sense amplifier, and invited an increase in the power consumption.
FIG. 13 shows the changes in the bit line voltage for the memory cell mat of the near end and far end when reading is performed. In the case of this example, the power supply voltage V.sub.DD is, for example, 3.3 V, and the lowered voltage V.sub.DL that is used within the memory array is, for example, 2.2 V. As is illustrated, before reading, the bit line BL and the complementary bit line BL- are precharged to a voltage level of one half of the internal power supply voltage V.sub.DL, for example, 1.1 V, and after starting reading, in response to the storage data of the memory cell, for example, the bit line BL- is charged by means of the power supply voltage V.sub.DD, and the complementary bit line BL is discharged by means of the common voltage V.sub.SS. Since the application time for the power supply voltage V.sub.DD to the bit lines BL in other words, the time T.sub.OVD for the overdrive is sent by matrixching it to the sense amplifier for the farthest end, the bit line that is connected to the sense amplifier for the farthest end is properly charged to the internal power supply voltage V.sub.DL by means of the overdrive operation, but at the bit line BL that is connected to the sense amplifier for the near end, it is charged to a surplus due to the same overdrive time T.sub.OVD, and when the overdrive is completed, is held at a level that is higher than the internal V.sub.DL. Since the complementary bit line BL.sub.-- is discharged by means of the common voltage V.sub.SS in the case of either the far end or the near end, its voltage is about the same.
This invention was made after reviewing this information, and its purpose is to offer a semiconductor memory device in which the timing for the overdrive can be controlled in response to the arrangement positions of the memory cell matrices, the bit lines can be driven at the optimum voltage, a reduction in the power consumption can be accomplished, and the timing design for the overdrive can be simplified.